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Semiconductor

GET TO MARKET FASTER

In the semiconductor industry, a single bug in the chip can lead to costly delays, product recalls, or even safety issues. Investment in shift-left techniques have helped to mitigate these risks by uncovering problems earlier in the semiconductor design process.

Behavioral models and High-Level Synthesis (HLS) have also enabled faster design cycles; but understanding and debugging these complex models can become a bottleneck.

By integrating time travel debugging capabilities into your design and verification flow, engineers get unprecedented visibility and access to the execution of HLS models—leading to faster time-to-market, improved design quality and increased productivity.

DEBUG ISSUES QUICKLY AND
GET TO MARKET FASTER

Challenges

Behavioral models are typically written in a high-level language such as SystemC.

But debugging SystemC models sucks!

  • SystemC designs are often opaque, concurrent, and can have many states—making it very difficult to root cause issues when then come up.
  • Using waveforms show what happened at the model boundaries, but it is often hard to track back to the root cause.
  • It can be hard to identify which model / component is causing the problem, making initial issue triage a challenge.

Solution

Undo helps address the challenges of debugging SystemC designs.

Undo’s time travel debugging capability allows your engineering team to record the execution of a failing test and replay the execution history of their HLS models.

  • Undo enables detailed signal values and data flow inspection at any point in the execution timeline, so engineers get full visibility into the dynamic behavior of the modelled hardware.
  • Engineers can quickly identify the root cause of issues from one run, without having to rebuild models or rerun scenarios multiple times.
  • Recording an intermittent failure turns it into a repeatable and deterministic recording, making root-cause analysis considerably easier.

SOLUTION

TIME TRAVEL DEBUGGING

Undo allows engineers to record the execution of their failing test and later step through the recording of their simulations not just forward, but backward, making tracking bugs easier.

Undo also provides several features that make it easier to visualize and understand SystemC designs, like one of our beta waveform viewers.

This workflow significantly reduces the time the team spends debugging.

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SOLUTION

ISOLATE CONCURRENCY BUGS

Concurrency bugs, such as deadlocks and race conditions, can take weeks to find using traditional techniques such as logging and forward-only debugging.

These kinds of bugs are pretty common in SystemC designs, where many threads can be accessing the same data and resources.

With time travel debugging we can isolate these issues very quickly.

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TRUSTED BY LEADERS

quote

We love the recording of our regression failures! It means we can quickly debug a test failure first thing in the morning, without having to spend an hour or more reproducing the problem ready to get started. This gets our regressions passing again sooner, reducing the time the rest of the team are blocked on submissions.

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HW engineers aren’t used to HLS debug and can get easily lost if there aren’t waveforms or some temporal view. Those who are familiar with setting breakpoints in GDB find the ability to step backward and forward in time really improves and accelerates their ability to solve bugs, leaving more time for quality and PPA improvements.

quote

We estimate our debug time on issues is reduced by about 4x. This productivity improvement gives us more time back to focus on closing coverage more completely, prior to tape-out.

quote

Concurrency bugs, such as deadlocks and race conditions, can take ages to find using traditional techniques such as logging and forward-only debugging. These kinds of bugs are pretty common in SystemC designs, where many threads can be accessing the same data and resources. With time travel debugging we can isolate these issues very quickly.
KEY BENEFITS

Significant cost savings all round

GET TO MARKET FASTER
Significantly reduce the time required to bring complex SoCs, ASICs, and associated software to market, by streamlining the debugging process.
BOOST ENGINEERING PRODUCTIVITY
Reduce the time your engineers spend on debugging, freeing them to focus on more value-added projects.
IMPROVE DESIGN QUALITY
Efficiently identify and fix bugs, leading to higher-quality designs with fewer defects.

Want to discuss if this could work in your environment?

Book a call with a Solutions Engineer

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